1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a function to alter the operating mode.
2. Description of the Background Art
At present, in general, in semiconductor integrated circuit devices produced, an operating mode is set in which one of two alternatives is selected where the representative examples of such selection include the selection between +5V and +3.3V for the operating power supply voltage, and the selection between the Fast Page mode (hereinafter referred to as the FP mode) and the Hyper Page mode (or the Extend Data Output mode, hereinafter referred to as the EDO mode).
When shipped, a semiconductor integrated circuit device has one of the two alternatives of an operating mode set according to the product specifications. It is desirable, however, to allow alteration of the operating mode with flexibility according to the state of production or the trend of market demands.
As an example of a technique that allows the switching of the operating mode of a semiconductor integrated circuit device according to changes in the state of production or the trend of market demands, a mode switching circuit is disclosed in the Japanese Patent Laying-Open No. 4-199541.
FIG. 17 is a circuit diagram of a prior art mode switching circuit 500.
As shown in FIG. 17, a mode switching circuit 500 includes an external input terminal 201 to which a voltage is applied externally for switching the mode, an external input pad 202 connected to external input terminal 201, a node 220 for outputting a control signal to switch the mode, a power supply line 204 for supplying a power supply voltage Vcc, a ground line 205 for supplying a ground potential Vss, an electric fuse 210 and resistive element 206 connected in series between power supply line 204 and node 220, and a resistive element 207 connected between ground line 205 and node 220.
Mode switching circuit 500 further includes an N-channel MOS transistor 203 having a gate connected to node 220 for connecting external input pad 202 with node 220.
In mode switching circuit 500, normally the resistance value ratio of resistive element 206 to resistive element 207 is determined such that the potential of node 220 is at the logic high or "H" level (Vcc). Here, N-channel MOS transistor 203 is designed to have a threshold voltage which allows the off state to be maintained even when external input terminal 201 is at the Vss level. Thus, under normal circumstances, external input terminal 201 and external input pad 202 are disconnected from node 220.
When switching the mode, a potential having a sufficient potential difference from the Vcc level is applied to external input terminal 201 to blow electric fuse 210. By blowing electric fuse 210, the potential of node 220 can be made to attain the logic low or "L" level (Vss) by resistive element 207, and thus the mode is switched.
Mode switching circuit 500 allows switching of the mode by having a voltage applied from outside to the memory device and having the electric fuse blown after the completion of the manufacturing process.
Thus, in a semiconductor integrated circuit device having a prior art mode switching circuit 500, it is possible to switch the mode by an operation performed from outside even after the manufacturing process is completed.
While the prior art mode switching circuit 500 allows switching of the operating mode after the completion of the manufacturing process, since an additional step of fuse blowing is required for the switching of the operating mode, alteration at a later time of an operating mode once determined at the stage of circuit design prior to the start of the manufacturing process may affect productivity, when, for instance, a great number of products must be subjected to such an alteration.
In addition, in the prior art mode switching circuit 500, since an electric fuse is blown by a current that flows through an MOS transistor and since the potential applied from outside to blow the fuse is also supplied to a node for generating a control signal, the internal circuit may be adversely affected, a successful fuse blow may not be ensured, and problems regarding performance reliability may arise.
Further, as to the above-mentioned MOS transistor, an MOS transistor having different characteristics from those of the other transistors in the semiconductor integrated circuit may be required to maintain the off state under normal conditions and to allow the passage of the fuse blow current when switching the mode. In such a case, the degree of freedom in layout designs could be limited.